This invention relates generally to high frequency signaling in packaged integrated circuits, and particularly to increasing the common mode rejection in high-frequency signals that use differential signaling.
A common method of providing input signaling in a semiconductor package is through the use of differential signaling using differential pair transmission lines. In differential pair transmission lines, there is a pair of conductors and usually a solid ground reference plane. Depending on the signaling mode, the signal being carried on the conductor pair and the ground reference plane changes. In a differential mode signaling, a pair of conductors is used for one signal, with a first conductor carrying a current into the load and a second conductor carrying a return current. The return current may be thought of as a current flowing away from the load. There is no current on the ground reference plane in differential signaling mode. The name differential signaling is derived from the fact that the information on the signal is transmitted as a difference of the two currents. In common mode signaling, the common mode signal is carried on both conductors (with half of the overall current on each conductor) and the common mode return current is carried on the ground reference plane. Should both differential and common mode signaling be used in a differential pair transmission line, the conductor pair will carry both common mode signal and the differential mode signal, while the ground reference plane will carry the common mode return current.
The pair of conductors used in differential signaling is commonly referred to as a differential pair transmission line or simply, a differential pair. Each differential pair may be characterized by its characteristic impedance. For example, the differential pair has an odd mode impedance, a differential mode impedance, and an even or common mode impedance. An odd mode or differential mode is defined by the current in one conductor of the differential pair being equal and opposite of the current in the other conductor of the differential pair, with no current being carried by the ground conductor. An even mode is defined by the current in both conductors of the pair being in the same direction and the current in the ground plane in the opposite direction. A differential pair""s odd mode impedance is defined as the ratio of voltage to current from one conductor to ground while its differential mode impedance is defined as the ratio of the voltage to current from one conductor to the other. Therefore, if one differential pair""s odd mode impedance is 50 ohms, then the pair""s differential impedance is two times the odd mode impedance, or 100 ohms, because the differential mode voltage is twice of the odd mode voltage. The even and common mode impedances are both defined as the impedance from one conductor to ground. Typically, a differential pair""s odd mode impedance is different from its even mode impedance.
In high-speed applications, the presence of signals clocked at different frequencies increases the overall ground and/or power plane noise. The problem with increased noise on the ground and/or power plane is that when the common mode impedance of the differential pair is similar to its differential mode impedance, then the noise on the ground and/or power plane is optimally coupled to the differential pair. The coupled noise appears as a common mode noise since it is present on both conductors of the differential pair. The input common mode rejection ratio (CMMR) of a differential receiver is frequency dependent and typically decreases with frequency. The CMMR of a differential receiver specifies the ability of the receiver to reject common mode noise. The presence of common mode noise on the differential pair decreases the maximum operating frequency of the circuit, which is limited by the input signal to noise ratio requirements for reliable signal detection. Generally, a high ratio of common mode impedance to differential mode impedance minimizes the ratio of common mode current to differential mode current for a given voltage. Thus, the higher the impedance ratio, the lower the coupling of the common mode noise on the ground and/or power plane to the differential pair.
Several different techniques have been used to help reduce the coupling of the ground and/or power plane noise to the differential pair. One technique specifies the use of ferrite chokes upon which the power plane signal is wrapped. While the ferrite chokes are effective at low signaling frequencies, their effectiveness rapidly drops as the signaling frequencies increase. Additionally, the ferrite chokes can be physically large, therefore limiting their usefulness in applications where minimal size is an important consideration.
Another frequently used technique involves the design of common mode termination impedances, which is used to reject the common mode noise. These techniques typically involve the use of capacitors that couple the differential pair to ground. The capacitors can significantly lower the termination impedance, hence improving the rejection of the noise. Unfortunately, the capacitors will also affect the differential mode impedance if the capacitance on each line of the pair is not carefully balanced. Additionally, the technique requires capacitors with fairly large capacitances to provide a sufficiently low impedance at the frequencies of interest. Large capacitors consume a large amount of real estate, therefore making size an important consideration. Finally, the use of capacitors results in a frequency dependent solution, since the impedance of the capacitors themselves will change with frequency.
Yet another technique increases the separation between the differential pair and the ground plane, i.e., increase the substrate thickness, thereby increasing the common mode impedance of the differential pair. This technique does not significantly affect the differential mode impedance, and therefore can be effective. However, with an increased ground plane separation, it is difficult to design non-differential mode impedances that are close to the system impedance. For example, with non-differential mode characteristic impedances of 50 ohms, the width of the conductors would become excessive, typically 1.2 times the substrate thickness. The large conductor width makes it difficult for packaging designers to route signals and yields an overall increase in the size of the packaging.
A need has therefore arisen for a technique to increase the common mode rejection in differential pairs without increasing the overall cost of the packaging.
One aspect of the present invention provides a substrate comprising a differential pair transmission line, an equi-potential plane with slots formed in the equi-potential plane, wherein the slots lie beneath the differential pair transmission line and are disposed perpendicularly to the differential pair transmission line""s orientation, and a dielectric layer positioned between the differential pair transmission line and the slotted equi-potential plane, the dielectric layer to electrically insulate the differential pair transmission line from the equi-potential plane.
Another aspect of the present invention provides a semiconductor chip comprising a substrate comprising a differential pair transmission line, an equi-potential plane with slots formed in the equi-potential plane, wherein the slots lie beneath the differential pair transmission line and are disposed perpendicularly to the differential pair transmission line""s orientation, a dielectric layer positioned between the differential pair transmission line and the slotted equi-potential plane, the dielectric layer to electrically insulate the differential pair transmission line from the equi-potential plane, and the semiconductor chip further comprising a package to hold the substrate, the package comprising a pad coupled to a pin on the package, the pad to provide electrical connectivity between the pin and the differential pair transmission line.
Another aspect of the present invention provides a method for forming a slotted ground plane, the method comprising the steps of forming an equi-potential plane, forming slots in the equi-potential plane, such that the slots run perpendicular to a differential pair transmission line, forming a dielectric layer on the equi-potential plane, and forming the differential pair transmission lines on the dielectric layer
The present invention provides a number of advantages. For example, use of a preferred embodiment of the present invention permits an increase in the rejection of common mode noise induced from power and/or ground planes without requiring changes to existing substrate manufacturing processes. Therefore, generally no engineering changes are required in the manufacturing steps that would increase costs.
Also, use of a preferred embodiment of the present invention permits the use of minimal substrate thickness, which is desired for minimizing ground bounce for non-differential mode signals and at the same time retaining good common mode rejection in differential mode signals.
Additionally, use of a preferred embodiment of the present invention does not compromise the line design for a specific characteristic impedance, for example, 50 ohms. This means that line widths are not changed, and routability of the lines is maintained.
Also, use of a preferred embodiment of the present invention permits the use of thinner substrates while maintaining the desired high impedance. Thinner substrates minimize the inductance for signal traces being used. Thinner substrates also allow the use of narrower traces for the non-differential signals and therefore increase package routability.